FIG. 1 is a partial schematic view of a prior art integrated circuit structure 400. As those in the art will recognize, an integrated circuit including a transistor or transistors and/or other devices (designated generally at 404) is formed over a silicon substrate 402 having a top surface 401 and a bottom surface 403. A contact etch stop layer (CESL) 405 is formed over the substrate top surface 401 along with a transistor structure and an oxide planarization structure 407. A metallization structure 406, including interconnects (i.e., lines and vias) and inter level dielectric layers (ILDs) is provided over the integrated circuit 404. Although only metal one (M1) and metal two (M2) metallization layers are illustrated, those in the art will understand that integrated circuits often have many more interconnect layers, dependent on device complexity, such as M1 to M9, formed between the device layer 404 and the passivation/bonding structure (not shown).
FIG. 2 is another view of integrated circuit structure 400, showing substrate layer 402 and interconnects layer 406. It should be understood that circuit layer 404, though not shown in FIG. 4, is formed over and/or in the top surface 401 of the substrate 402. A wire bond 408 is shown in partial. Wire bond(s) 408 or conductive bump(s) for flip chip bonding is formed over and connected to the topmost metal layer of interconnect structure 406 as is familiar to those in the art, often through one or more passivation layers.
It is advantageous to use inter level dielectric layers in interconnect structure 406 that are formed from low-K (LK), ultra low-K (ULK), extra low-K (ELK) and XLK materials (collectively, “low-K” dielectric material) in order to gain circuit performance, such as reductions in capacitances between interconnect lines, and thus crosstalk. The material classification is based upon capacitance or k value, with LK usually referring to those materials with a k between about 3.1 to 2.7, ULK usually referring to those materials with a k between about 2.7 to 2.4, and ELK usually referring to those materials with a k between about 2.3 to 2.0. XLK refers to a porous HSQ-based dielectric material available from Dow Corning Corporation (Midland, Mich.) which typically has a k value less than about 2.0. These low K dielectrics, however, have poor mechanical strength and thus tend to crack under stresses induced during bonding techniques, e.g., formation of wire bonds 408 or conductive bumps. Further, mechanical strength, and thus the instances of cracking, deteriorates with increased numbers of metallization layers in interconnect structure 406. Further, with increased numbers of layers, connection wire lengths increase yielding higher resistance (R), and thus higher RC delay, which lowers the device speed.
Therefore, an improved interconnect structure and method of forming the same are desired.